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IDProjectCategoryView StatusLast Update
0002377SystemVerilog P1800SV-BCpublic2008-11-17 08:13
ReporterShalom Bresticker Assigned To 
PrioritynormalSeveritymajorReproducibilityalways
Status newResolutionopen 
Product VersionP1800-2008/D5 
Fixed in Version 
Summary0002377: 6.22.3: incorrect xref for implicit casting
Description

In P1800-2009/D5, 6.22.3 says,

"Implicit casting rules are defined in 6.24."

But 6.24 does not define implicit casting rules.

TagsNo tags attached.
TypeErrata

Relationships

child of 0002314 new Master issue for SV-BC Casting issues 

Activities

Shalom Bresticker

Shalom Bresticker

2008-11-17 08:13

developer   Note 0007706

In fact, implicit casting is not defined anywhere in the LRM, only referenced. Implicit casting is referenced in the following places in Draft 7a:

6.22.3: "All equivalent types, and all nonequivalent types that have implicit casting rules defined between them, are assignment-compatible types."

"Implicit casting rules are defined in 6.24."

6.24.1: "Thus, an implicit cast (e.g., temp1 = expr1), if defined, gives the same results as the corresponding explicit cast (cast_t1'(expr1))."

7.9.4: "The index expression shall be evaluated in terms of a cast to the index type, except that an implicit cast from a real or shortreal data type shall be illegal."

11.11: "The exception is if the actual argument is an integral type and there is only one prototype with a corresponding integral argument, in which case the normal implicit casting rules apply when calling the function."

Issue History

Date Modified Username Field Change
2008-05-06 10:15 Shalom Bresticker New Issue
2008-05-06 10:15 Shalom Bresticker Type => Errata
2008-05-13 07:49 Shalom Bresticker Relationship added child of 0002314
2008-11-17 08:13 Shalom Bresticker Note Added: 0007706
2008-11-17 08:13 Shalom Bresticker Severity minor => major